Chemical-mechanical polishing (“CMP”) is a technology which has its roots in the pre-industrial era. In recent years, CMP has become the technology of choice among semiconductor chip fabricators to planarize the surface of semiconductor chips as circuit pattern layers are laid down. CMP technology is well known, and is typically accomplished using a polishing pad and a slurry or composition which contains chemical reagents and abrasive particles. The chemical reagents function to chemically react with the surface of the layer being polished whereas the abrasive particles perform a mechanical grinding function.
The fabrication of semiconductor wafers typically involves the formation of a plurality of integrated circuits on a semiconductor substrate of, for example, silicon or gallium arsenide. The integrated circuits are generally formed by means of a series of process steps in which patterned layers of materials, such as conductive, insulating and semiconducting materials, are formed on the substrate. In order to maximize the density of integrated circuits per wafer, it is necessary to have an extremely planar precision polished substrate at various stages throughout the semiconductor wafer production process. As such, semiconductor wafer production typically involves at least one, and more typically a plurality of polishing steps, which involve the use of one or more polishing compositions.
The polishing steps typically involve rotating or rubbing the polishing pad and/or semiconductor wafer substrate against each other in the presence of a polishing fluid or composition, usually using a controlled and repetitive motion. The polishing fluid is often mildly alkaline and may optionally contain abrasive particulate materials, e.g., silica. The pad acts to mechanically polish the semiconductor substrate, while the polishing fluid serves to chemically polish the substrate and to facilitate the removal and transport of abraded material off of and away from the rough surface of the article. Typically, a polishing fluid is interposed between the rough surface of the article that is to be polished and the work surface of the polishing pad. The polishing fluid may optionally contain an abrasive material, e.g., particulate cerium oxide.
Chemical-mechanical polishing is commonly used for the polishing of integrated circuits, wherein the chemical agents modify low-lying surfaces and protect them from abrasion and the mechanical agents remove the material to be removed. Polishing can be used to remove either metals or dielectrics in the electronics industry, as well as other materials.
In the case of the removal of a dielectrics or oxides, most conventional CMP slurries used for polishing oxides typically comprise abrasive particles dispersed in an aqueous alkaline medium (i.e., high pH). In some cases, it is desirable to selective polish silicon dioxide compared to silicone nitride. A few CMP slurries are known which do provide a fairly high silicon dioxide to silicon nitride removal rate selectivity. See for example, Srinivasan et al. U.S. Pat. No. 6,491,843, Hosali et al., U.S. Pat. No. 5,738,800; Grover et al., U.S. Pat. No. 5,759,917; Kodama et al, EP 0 786 504 A2; Ronay, EP 0 846 740 A1; and Morrison et al., and EP 0 853 335 A2.
U.S. Patent Publication 2002/0173243 discloses a polishing composition useful for removing excess metal, typically peaks of copper from a semiconductor substrate comprising a wafer and multiple layers of material, including a layer of insulating material, that is deposited and provided with troughs and a metal conductor that is deposited as a layer and is in the troughs to form a copper circuit. The composition comprises organic polymer particles as abrasive particles. Copper is cleared from the surface of the substrate or wafer, with minimized, i.e., substantial reduction in, dishing of the copper circuit. Planarization in this publication refers to clearing the copper layer from the semiconductor substrate with minimized dishing of the copper in the troughs. Planarized refers to a flat polished surface of the semiconductor substrate, and the copper in the troughs having minimized dishing, resulting from a process of CMP that has removed the copper layer.
U.S. Pat. No. 6,454,819 to Yano et al (JSR corporation) discloses a CMP slurry wherein a silicon compound section or metal compound section is provided in the polymer particles to give the surface thereof adequate strength and hardness, excellent heat resistance and suitable flexibility and to increase the polishing rate while also preventing scratches, and by providing a process for manufacture of semiconductor devices using the CMP slurry. The CMP slurry is useful for chemical mechanical polishing in the manufacture of semiconductor devices, and especially chemical mechanical polishing of wafer surfaces. The polymer particles have at least one siloxane-bond-containing section and a metal compound section on the particles. The metal compound can be alumina, ceria, or zirconia.
U.S. Pat. No. 2002/0006728 A1 to Matsui et al. disclose a slurry for CMP comprising a liquid and a plurality of polishing particles, wherein the polishing particle contains an organic particle and a plurality of inorganic particles unified by thermocompression bonding. Preferably, the inorganic particles are manganese dioxide and/or ceria.
EP 1243611 to Nisimoto et al. discloses an aqueous dispersion for chemical mechanical polishing comprising composite particles formed by changing the zeta potential of polymer particles and inorganic particles so they are opposite in sign. The inorganic particles include alumina, titania, and ceria.